The present invention relates to semiconductor devices and methods of forming the same. More specifically, the present invention is directed to a semiconductor device with a semiconductor chip and a method of forming the same.
A semiconductor fabricating process may be categorized into two processes: a front-end process and a back-end process. In the front-end process, semiconductor chips are formed on a wafer by means of photolithography, etching, and/or deposition. In the back-end process, the semiconductor chips are packaged.
A conventional semiconductor package generally includes only one semiconductor chip. However, multi-functional semiconductor packages and highly integrated semiconductor packages have been required with the remarkable advance in electronic technologies. In recent years, stacked packages have been suggested for multi-functionality and high integration. The stacked package includes a plurality of semiconductor chips. Conventionally, terminals of such stacked semiconductor chips are coupled to each other or coupled to an external terminal by means of wire bonding technology. Unfortunately, various problems are encountered when the wire bonding technology is employed to couple stacked semiconductor chips. For example, the basic length and structure of bonding wire itself can make it difficult to reduce the size of a package and generally results in signal delay caused by the electrical properties of the wire. Moreover, terminals of the stacked semiconductor chips generally need to be exposed for wire bonding. Thus, the sizes of the stacked semiconductor chips may be varied to accommodate the wire bonding coupling, which usually leads to increases in the size of the package. In addition, the wire bonding may complicate fabrication because of the difficulty in stacking the semiconductor chips while accommodating the space necessary for the wire bonding.